Integrated circuit device tester

ABSTRACT

In an IC device tester for testing IC devices held in contact with a test head, optical signals are employed for all signal exchanges between a tester mainframe and the test head and signal transmission lines therebetween are all formed by optical fibers, whereby the cable group interconnecting the tester mainframe and the test head can be made small in diameter and can be extended as required.

BACKGROUND OF THE INVENTION

The present invention relates to an integrated circuit device tester fortesting semiconductor integrated circuit devices (ICs) or large-scaleintegrated circuit devices (LSIs).

In FIG. 1 there is shown in block form the general configuration of anintegrated circuit device tester in wide use. Reference numeral 100denotes a test head and 200 a tester main frame. The test head 100 has aperformance board 101 and a pin electronics 102 mounted thereon. Theperformance board 101 has a socket (not shown in particular) for contactwith a device under test (hereinafter referred to as a DUT) to establishtherethrough electric connections between it and the tester.

The pin electronics 102 has a driver group 103 for electrically drivingthe DUT, an analog comparator group 104 for checking response outputsignals read out of the DUT to determine if their H and L logic havenormal voltage values, and a relay matrix 105 for switching the devicegroups that are connected to respective terminals of the DUT.

The tester main frame has a pattern generator 201, from which testpattern data (a digital signal) is output. The test pattern data and atiming edge signal from a timing generator are applied to a formatter202, by which a pattern signal (a signal having an analog waveform) tobe applied to each terminal of the DUT is generated. The pattern signalis provided via a pattern transmission line 301 to the test head 100,wherein it is applied via the driver group 103 to each terminals of theDUT. Incidentally, a timing signal is also contained in the patternsignal that is sent over the pattern transmission line 103.

The comparison results by the analog comparator group 104 are sent viaresponse signal transmission lines 302 back to the tester main frame200, wherein they are logically compared by a logical comparator 203with expectation patterns from the pattern generator 201 to detect amismatch between them and consequently a failing part. Reference numeral204 denotes a failure memory, in which upon each detection of a mismatchby the logical comparator 203, H or L logic representing a failure iswritten at an address where the failure occurred.

Reference numeral 205 denotes a timing generator. As regards the timinggenerator 205, the presence of a coarse delay circuit DY1 and a finedelay circuit DY2 will be described first, for convenience of describinglater on that, according to the present invention, they are separatelyprovided in the tester main frame 200 and the test head 100,respectively.

Conventionally, the timing generator 204 frequency-divides a referenceclock CLK, shown in FIG. 2, Row A, to obtain a rate pulse RAT (FIG. 2,Row B) that determines the test period or cycle T; besides, the timinggenerator 204 delays the rate pulse RAT by arbitrary time intervals togenerate various timing signals such as the rise and fall timing of thetest pattern signal waveform, the strobe timing of the analog comparatorgroup 104 and the timing for the comparing operation of the logiccomparator 203.

Accordingly, the timing generator 202 has a number of delay circuits bywhich the rate pulse RATE can be delayed for arbitrary periods of timewithin the range of the test period T or within a several-fold range;these delay circuits are used to generate various timing signals whichare delayed behind the reference timing by arbitrary time intervals,such as timing signals T1 and T2 shown in FIG. 2, Rows C and D.

These delay circuits in the timing generator 205 are formed bycombinations of coarse delay circuits DY1 each of which counts the clockpulses CLK and provides a delay time in units of the period τ1 of theclock CLK and fine delay circuits DY2 each of which subdivides the rangeof the period τ1 of the clock CLK to define a delay time; these delaycircuits define the rise and fall timing of the test pattern signal byresolution on the order of picoseconds, for instance.

The tester main frame 200 further includes a DC test unit 206, a loadtest unit 207, a first reference voltage source 208 for setting voltagevalues VIH and VIL of H and L logic of the pattern signal, a secondreference voltage source 209 for supplying comparison voltages VOH andVOL to the analog comparator group 104, and a power supply unit 211 forapplying voltage to the DUT for operation. The setting and operation ofthe DC test unit 206, the load test unit 207, the first and secondreference voltage sources 208 and 209 and the power supply unit 211 arecontrolled entirely by a control processor 10 via a control bus 11,together with setting and operation of the pattern generator 201, theformatter 202, the failure memory 204 and the timing generator 205.

FIG. 3 schematically shows the connection between the test head 100 andthe tester main frame 200. The tester main frame 200 and the test head100 are interconnected via a cable group 300. Since the tester mainframe 200 and the test head 100 are interconnected via various signalslines as referred to previously with reference to FIG. 1, the number ofcables housed in the cable group 300 is large.

There is a tendency that the number of IC terminals increases with anincrease in the integration density of ICs. The speeding-up of ICoperations also causes an increase in the number of cables of the cablegroup 300 that interconnects the tester main frame 200 and the test head100. In a tester having a test capacity corresponding to, for example,1000 IC terminals, the number of signals that are exchanged between thetester main frame 200 and the test head 100 is as large as tens ofthousands; in addition, since twisted-pair, coaxial, multi-sealed andsimilar special cables are used taking into account high speed, highaccuracy, noise resistance and so forth, the actual number of conductorsis several times larger than the number of signals handled and the cablegroup 300 forms a big bundle accordingly, making it difficult to movethe test head 100 (for mounting thereon or dismounting therefrom ahandler, for instance).

Another disadvantage of the prior art is that even a slight increase inthe length of the cable group 300 causes crosstalk between the cables,resulting in the test accuracy being impaired. Moreover, thetransmission of such a large number of signals consumes much power,which means an increase in the amount of heat generated and hence makescooling hard, and the number of terminating resistors also increases.These factors constitute an obstacle to downsizing of the system.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide anintegrated circuit device tester which permits suppression of crosstalkbetween signals as well as allows ease in handling the test head throughminimization of the cable group interconnecting the tester mainframe andthe test head.

According to the present invention, there is provided an IC devicetester which, under the control of a control processor, generatespattern data and expectation data by a pattern generator, formats thepattern data by a formatter into a predetermined pattern waveform,applies the pattern waveform by a driver to an IC device under test at areference voltage, compares the response signal from the IC device undertest by an analog comparator with a reference logical level to make alogical decision, compares the decided logic by a logic comparator withthe expectation data from the pattern generator to decide whether or notthe IC under test is defective or nondefective, and writes failure datain a failure memory. The IC device tester comprises:

a tester mainframe provided with the control processor;

first serial data transceiver means provided in the tester mainframe,for outputting data, as serial data, which is used to set the referencevoltage for the driver and the reference logical level for the analogcomparator;

electro-optic converter means provided in the tester mainframe, forconverting the serial data to a lightwave signal;

a test head provided with the driver for applying a test pattern to theIC device under test and an analog comparator for deciding the logic ofits response;

opto-electric converter means provided in the test head, for convertingthe lightwave signal to electrical serial data;

second serial data transceiver means provided in the test head, forconverting the serial data to parallel reference voltage data andparallel reference logical level data;

D/A converter means for converting the parallel reference voltage dataand the parallel reference logical level data to an analog referencevoltage and a reference logical level and for setting them in the analogcomparator and the logic comparator, respectively; and

optical fiber means for interconnecting the electro-optic convertermeans and the opto-electric converter means.

According to the present invention, it is possible to employ aconfiguration wherein data or various timing signals set for each ICterminal, which are sent from the tester mainframe to the test head, aretransmitted as optical serial signal, received and converted by theserial data transceiver means in the test head into parallel signals forstorage in setting register means, and measured data and measuredresults are sent as lightwave signals back to the tester mainframe.

According to the present invention, the test head is further providedwith a pattern memory and a formatter and digital test pattern data bythe pattern generator is sent as an optical serial signal to the testhead for storage in the pattern memory. At the same time as the teststarts, the test pattern data stored in the pattern memory is read outtherefrom, then the read-out test pattern data (a digital signal) isformatted by the formatter to an analog pattern signal, and the patternsignal is applied via the driver to the IC device under test.

With the configuration of the present invention, the opticaltransmission line is about 200 to 500 mμφ in diameter even if a plasticoptical fiber is used therefor, and unlike in the case of transmittingelectric signals, a two-way conductor is not needed for each channel;hence, the signal transmission line can be reduced in diameter and inweight. With the configuration that transmits and receives opticalserial signals, the number of optical fibers used can be madeparticularly small and the cable group can be made furthersmall-diametered and lightweight. Moreover, since the optical fibertransmits light only along its central portion, no crosstalk occurs.Accordingly, the length of cable group can be made long.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram for explaining the prior art;

FIG. 2 is a waveform diagram for explaining the operation of the priorart;

FIG. 3 is a perspective view for explaining the prior art;

FIG. 4 is a block diagram illustrating an embodiment of the presentinvention;

FIG. 5 is a block diagram illustrating an example of the pin unitconfiguration in FIG. 4;

FIG. 6 is a perspective view for explaining an example of the pin unitstructure used in the embodiment of FIG. 5;

FIG. 7 is a perspective view for explaining an example of a structurefor mounting the pin unit shown in FIG. 6;

FIG. 8 is a sectional view for explaining an example of an opto-electriccompound board depicted in FIG. 7;

FIG. 9 is a block diagram illustrating another embodiment of the presentinvention;

FIG. 10 is a block diagram showing an example of the pin unit structurein the embodiment of FIG. 9;

FIG. 11 is a block diagram illustrating still another embodiment of thepresent invention; and

FIG. 12 Is a block diagram showing an example of the pin unit structurein the embodiment of FIG. 11.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 4 illustrates in block form an embodiment of the IC device testeraccording to the present invention. The present invention uses anoptical fiber cable and a power supply wire cable to interconnect thetester mainframe 200 and the test head 100. The use of the optical fibercables permits transfer of various test data, transfer of various setdata and transmission of various timing signals. By limiting the use ofthe wire cable only to power supply and by using the optical fiber cablefor as many connections as possible, the volume of the connection cablebetween the tester mainframe 200 and the test head 100 can be reduced.

In this embodiment, the DC test unit 206, the load test unit 207 and thefirst reference voltage source 208 provided in the tester mainframe 200in FIG. 1 are shifted as their counterparts to the test head 100, and aserial data transceiver 212 and an optical input/output (I/O) module 213are provided in the tester mainframe 200. On the other hand, a pin unit110 is provided in the test head 100 as will be described later on withreference to FIG. 5. The pin unit 110 is equipped with the functions ofthe DC test unit, the load test unit and the first reference voltagesource as well as pin electronics. The optical I/O module 213 haselectro-optic converters 2EO1 to 2EO5 and opto-electric converters 2OE1to 2OE5. The optical I/O module 213 is connected to the pin unit 110 ofthe test head 100 via optical fibers OPF1 to OPF10 and an opticalcoupling part 126.

The serial data transceiver 212 outputs and provides various set voltagedata, load test conditions, DC test set data, relay matrix control data,etc. to the electro-optic converter 2EO1 and receives via theopto-electric converter 2OE1 DC test result data TX from the test head100. The formatter 202 formats the test data pattern fed thereto into apredetermined form and provides it to the test head 100 via theelectro-optic converter 2EO2. The timing generator 205 applies a timingedge signal to the formatter 202 and generates and sends strobe signalsSTRB-H and STRB-L to the electro-optic converters 2EO4 and 2EO5, fromwhich they are applied as optical strobe signals to the test head 100.The logic comparator 203 receives the test results (logical dataobtained by deciding the results of analog comparison at the strobetiming) from the test head 100 converted by the opto-electric converters2OE4 and 2OE5 into electric signals, then compares them with expectationdata EPD to decide whether or not the IC device under test (hereinafterreferred to as a DUT) is nondefective, and write failure data in thefailure memory 204.

FIG. 5 illustrates in block form the configuration of the pin unit 110in the FIG. 4 embodiment, which supplies a pattern signal to oneterminal P of the DUT and makes an analog comparison of a signal outputfrom the terminal P and sends the comparison result to the testmainframe 200.

The pin unit 110 comprises, in this example, a pin electronics 102Aloaded with a driver 103A for driving one terminal P of the DUT, ananalog comparator 104A and a load test circuit 117, a relay matrix 105,a local pin controller 111, a DC test unit 116 and an optical I/O module113.

The optical I/O module 113 has opto-electric converters OE1 to OE5 andelectro-optic converters EO1 to EO5 and converts optical signals fromthe tester mainframe 200 by the opto-electric converters OE1 to OE5 intoelectric signals, which are used to run functional and DC tests.

The local pin controller 111 is made up of: a serial data transceiver111A for receiving a serial signal sent from the optical fiber OPF1 viathe opto-electric converter OE1; register groups 111B, 111C and 111Dwhich read therein serial data for various setting, received by theserial data transceiver 111A, and output it as parallel data for varioussetting use; a D/A converter 11E for generating from the setting data,for example, voltages VIH and VIL for the driver 103A and comparisonvoltages VOH and VOL for the analog comparator 104A; and a relay controlcircuit 111F for controlling the relay matrix 105 based on the paralleldata for relay control use from the register group 111D.

That is to say, voltage values of the voltage VIH of H logic and thevoltage VIL of L logic for the driver 103A and the comparison voltagesVOH and VOL for the analog comparator 104A are stored in the registergroup 111B, from which they are provided as parallel data to the D/Aconverter 111E for conversion into analog voltage values, which areprovided to the driver 103A and the analog comparator 104A. Further,test conditions for operating the load test circuit 117 are also storedin the register group 111B, and the data read in the register group 111Bis used for the load test, too.

Stored in the register group 111C are control signals necessary for theDC test which, for example, in the test mode (voltage-applied currentmeasuring mode/current-applied voltage measuring mode), control settingof the applied voltage/current value, setting of the measuring range,the start and stop of the measurements, and so on, and DC test results.As required, the test results are transmitted to the tester mainframe200 after being sent via the serial data transceiver 111A to andconverted by the electro-optic converter EO1 into an optical signal TX.

Stored in the register group 111D is a control signal for controllingthe relay matrix 105. The control signal is input into the relay controlcircuit 111F to control the pin electronics 102A and the relay matrix105 to put them in the state corresponding to the test mode being set.That is, during the operation test, the driver 103A and the analogcomparator 104A are connected to the terminal P of the DUT and the DCtest unit 116 is disconnected therefrom. During the DC test, the pinelectronics 102A is disconnected from the pin P of the DUT but insteadthe DC unit 116 is connected thereto.

In this way, the local pin controller 111 sets in the register groups111B, 111C and 111D the conditions to be set for each terminal Paccording to test modes. Since the data to be stored in the registergroups 111B, 111C and 111D is sent as an optical serial signal RX, onlyone optical fiber OPF1 is enough as the transmission line therefor, andthe optical signal RX sent over the optical fiber OPF1 is converted bythe opto-electric converter OE1 to an electric signal, which is inputinto the serial data transceiver 111A.

In this example, the data for various setting, stored in the registergroups 111B, 111C and 111D is read out therefrom, as required, andconverted by the electro-optic converter EO1 into the optical signal TX,which is sent via the optical fiber OPF2 back to the tester mainframe200, wherein a check is made to see if the tester is correctly set.

The optical fiber OPF3 forms a pattern signal transmission line, overwhich the pattern signal to be applied to the terminal P is sent as anoptical signal PAT. The pattern signal PAT is converted by theopto-electric converter OE2 into an electric signal, which is applied tothe driver 103A mounted in the pin electronics 102A and thence to theterminal P.

Transmitted over the optical fiber OPF4 is a driver control signal DREwhich is used to control the state of the driver 103A during afunctional test. In the case of taking out the response signal from theDUT, the output terminal of the driver 103A is controlled by thecontrolled signal DRE to be high-impedance so that the response outputsignal can effectively read into the analog comparator 104A.

The optical fibers OPF5 and OPF6 form transmission lines over whichstrobe pulses for defining the timing of comparison of H- and L-logiclevels in the analog comparator 104A are sent as optical signals STRB-Hand STRB-L, respectively. The optical signal STRB-H is a pulse forstrobing the H-logic period of a signal that is read out of the DUT andthe optical signal STRB-L a pulse for strobing the L-logic period of theread-out signal.

These optical signals STRB-H and STRB-L are converted by theopto-electric converters OE5 and OE6 into electric signals, which areapplied as strobe pulses to the analog comparator 104A.

The optical fibers OPF7 and OPF8 form transmission lines over whichstrobe pulses are send back to the tester mainframe 200 from the testhead 100. The strobe pulses RSTRB-H and RSTRB-L that are sent back tothe tester mainframe 200 are given by the actual circuit arrangement adelay time during which they travel between the tester mainframe 200 andthe analog comparator 104A and they are used as strobe pulses for alogic comparator provided in the tester mainframe 200. That is, thedecision results from the analog comparator 104A are sent over theoptical fibers OPF7 and OPF8 to the tester mainframe 200 after beingconverted to optical signals and input into the logical comparator; inthis instance, to make the delay time of the transmission of thedecision results and the delay time of the strobe pulses coincide witheach other, the strobe pulses are made to travel between the testermainframe 200 and the test head 100. The optical fibers OPF9 and OPF 10serve as transmission lines over which the decision results from theanalog comparator 104A, that is, the functional test results of the DUTin this example, are sent as SH and SL back to the tester mainframe 200.

As will be seen from the above, the embodiment of FIG. 4 permitsimplementation of signal exchanges between the tester mainframe 200 andthe test head 100 by means of 10 optical fibers for each terminal P ofthe DUT. Even if plastic optical fiber of a relatively large diameter asof 500 mμφ is used, a bundle of 10 optical fibers is very small indiameter and even a bundle of as many as 10,000 optical fibers for 1,000IC terminals is sufficiently smaller in diameter than the electric cablegroup 300 (see FIG. 3). While in the above the return strobe pulsesRSTRB-H and RSTRB-L are used to provide the timing for comparison by thelogic comparator 203, it is also possible to generate the logicalcomparison timing by the timing generator 205 and provide it to thelogic comparator 203 as indicated by the broken line, in which case theoptical fibers OPF7 and OPF8 are unnecessary and the number of opticalfibers used can be reduced accordingly. Alternatively, it is possible toadopt a construction wherein a mere analog comparator with no latchfunction is used as the analog comparator 104A of the test head 100 andhence is caused to successively perform the comparison without applyingthereto the strobes STRB-H and STRB-L, then the comparison results aresampled at the tester mainframe 200 side at the timing of the strobesSTRB-H and STRB-L, and the sampled data is provided to the logiccomparator 203.

FIG. 6 shows the structure of the pin unit 110 into which the respectivecomponents shown in FIG. 5 are assembled together for each pin of theDUT. On a wiring board 110B in the case 110A there are mounted anintegrated circuit element forming the local pin controller 111, anintegrated circuit element forming the DC test unit 116, the pinelectronics 102A loaded with the driver 103A, the analog comparator 104Aand the load test circuit 117, the relay matrix 105, the optical I/Omodule 113, an electrical connector 114 for power supply, and aconnector 115 for connection to or disconnection from the performanceboard. Reference numeral 112 denotes a radiation block.

FIG. 7 illustrates an example of a structure for mounting the pin unit110 on the test head 100. Reference numeral 121 denotes an opto-electriccompound board. The opto-electric compound board 121 has such aconstruction as shown in FIG. 8. A multi-layered electric wiring layer122 has in its one surface an optical-fiber embedded layer 123 in whichoptical fibers OPF are embedded therein side by side with their innerends cut at 45 degrees as indicated by S1; the oblique end face of eachoptical fiber is directed toward the electric wiring layer 122 so thatlight propagating over the optical fiber is reflected off in thedirection perpendicular to the wiring board surface, and the optical I/Omodule 113 mounted in the pin unit 110 (FIG. 6) is placed in thedirection of reflection to establish optical coupling between theoptical fiber OPF and the optical I/O module 113 of the pin unit 110.

The optical fiber OPF has its other end exposed at the end face of thewiring board. By optically coupling an optical fiber cable 124 (see FIG.7) extended from the tester mainframe 200 (not shown in particular inFIG. 7) to the exposed end face S2 of the optical fiber OPF, the testermainframe 200 and the pin unit 110 provided at the side of the test head100 can be connected via an optical transmission line. Incidentally, theelectric connector 114 mounted in the pin unit 110 (FIG. 6) iselectrically connected via an ordinary electric connection structure tothe electric wiring layer 122, through which it is connected to thetester mainframe 200.

In FIG. 7, reference numeral 125 denotes an electric cable for powersupply use which is extended from the tester mainframe 200, 126 anoptical coupling part formed in the surface of the opto-electriccompound board 121, and 127 an electric connector. By connecting theoptical I/O module 113 and the electric connector 114 of the pin unit110 to the optical coupling part 126 and the electric connector 127,respectively, the pin unit 110 is connected to the tester mainframe 200.

Large numbers of optical coupling parts 126 and electric connectors 127are formed in the surface of the opto-electric compound board 121 sothat a desired number of pin units 110 can be mounted thereon. While inthe above the opto-electric compound board 121 has been described to beused for the interconnection of the pin unit 110 and the optical fibercable 124, the opto-electric compound board 121 need not always beemployed, in which case the pin unit 110 and the optical fiber cable 124may be interconnected via an optical connector that is mounted in thesurface of the electric wiring layer. Alternatively, the optical fibercable 124 and the electric cable 125 may be connected directly to thepin unit 110 by connecting an optical connector and an electricconnector to the end portions of the optical fiber cable 124 and theelectric cable 125, respectively.

Reference numeral 128 in FIG. 7 denotes a cooling frame whichmechanically supports the pin unit 110 and at the same time has afunction of cooling it. The cooling frame 128 has a number of unithousing holes 128A, which are each surrounded, for example, bydouble-structured walls that define therebetween a passage for cooingwater. Reference numerals denote cooling water inlet and outlet ports,respectively.

On the top end face of the pin unit 110 there are planted uprightelectric connectors, through which the pin unit 110 is electricallyconnected to the performance board 101. Incidentally, FIG. 7 shows thecase where plural pin units 110-A are mounted directly on the top of theperformance board 101 with a view to minimizing the length of electricwiring for their connection to IC devices under test; hence, thisconfiguration is particularly suitable for testing high-speed ICdevices.

FIG. 9 illustrates another embodiment of the present invention. In thisembodiment the formatter 202 and the logic comparator 203 provided inthe tester mainframe 200 in the FIG. 4 embodiment are removed therefromto the test head 100 to eliminate the need for exchanging the strobesignals between the tester mainframe 200 and the test head 100 and hencereduced the number of optical fibers used correspondingly. Accordingly,pattern data PAD generated by the pattern generator 201 is converted bythe electro-optic converter 2EO2 into an optical signal, which isapplied via the optical fiber OPF3 to the pin unit 110 of the test head100, and in a waveform or format controller 130 shown in FIG. 10 thetest pattern signal of a real waveform is generated from the patterndata PAD and applied to the DUT. The response signal from the DUT iscompared with an expected value in the pin unit 110 and the comparisonresults (failure data) FDAT are converted into an optical signal, whichis sent over the optical fiber OPF7 to the mainframe 200, wherein it iswritten in the failure memory 204 after being converted by theopto-electric converter 2OE2 into an electric signal.

Fine control of the delay time for the timing generator 205 in FIG. 4,which is shorter than the clock period, is effected at the test headside. The timing generator 205 generates the clock signal CLK, the ratesignal RATE subjected to delay control in units of the clock period andfine delay control data DCT for fine delay control, which are convertedby the electro-optic converters 2EO4, 2EO5 and 2EO3 into opticalsignals, and these optical signals are supplied to the test head 100 viathe optical fibers OPF5, OPF6 and OPF4.

As shown in FIG. 10, the test head 100 is provided with the waveform orformat controller 130 as well as the local pin controller 111 and the DCtest unit 116 and is so configured as to generate a pattern signal andperform a logical comparison operation by the format controller 130.That is, the format controller 130 is also provided with a serial datatransceiver 131, which receives a serial signal of the test pattern dataPAD sent over the optical fiber OPF3 from the pattern generator 201(FIG. 9) and applies it to the formatter 132, wherein a pattern signalof an analog waveform is generated.

With a view to avoiding upsizing of the test head 100, only the finedelay circuit DY1, referred to previously with reference to FIG. 1, isremoved from a timing generator 133 to the test head side to reduce thecircuit scale of the timing generator 133 in the test head 100.Accordingly, in this example the rate pulse, coarsely delayed by thecoarse delay circuit DY1 in units of the clock period at the testermainframe 200, is converted by the electro-optic converter 2EO5 into anoptical signal and this optical rate pulse RATE is sent over the opticalfiber OPF4 to the pin unit 110. This optical signal is converted by theopto-electric converter OE3 into the rate pulse RATE and applied as anelectric rate pulse RATE to the timing generator 133, wherein it isfinely delayed and distributed therefrom as timing signal to respectiveparts. The fine delay control data DCT is input into a timing controller135 from the optical fiber OPF5 via the serial data transceiver 131. Thefine delay control data DCT is used to control the timing generator 133by the timing controller 135.

A logic comparator 134 makes a logical comparison between the testpattern data PAD (a digital signal) input into the formatter 132 and theresponse signal from the DUT and sends the comparison result as afailure signal FDAT to the serial data transceiver 131, from which it issent to the electro-optic converter EO5 for conversion into an opticalsignal, which is sent over the optical fiber OPF7.

FIG. 11 illustrates in block form still another embodiment of thepresent invention. In this embodiment the pattern generator 201, thefailure memory 204 and the timing generator 205 are further removed tothe test head side in the FIG. 9 embodiment and a serial datatransceiver 214 is added to the tester mainframe 200 and is soconfigured as to transmit data necessary for pattern generation via theoptical fiber OPF4 and receive the test results via the optical fiberOPF5. With this configuration, the total number of optical fibers usedis smaller than in the FIG. 9 embodiment.

With the view of generating a pattern signal at the test head side, thepin unit 110 of the test head 100 in this embodiment is provided, asdepicted in FIG. 12, with a timing memory 141, a pattern memory 142 andfailure memory 143 in association with the format controller 130.

The serial data transceiver 214 sends, in advance, pattern data RXX as aserial signal via the optical fiber OPF4 to the pattern memory 142 forstorage therein. Furthermore, the serial data transceiver 214 utilizesan idle time to send the delay control data (timing data) DCT via theoptical fiber OPF5 to the timing memory 141 for storage therein. Hence,prior to the start of test, data for all terminals of the DUT is sentfrom the tester mainframe 200 to the respective pin units 110 providedin the test head 100 for storage.

At the same time as the test starts, the pattern data PAD is read outfrom the pattern memory 142 and is provided to the formatter 132 forconversion into a pattern signal of an analog waveform. The delaycontrol data DCT is also read out of the timing memory simultaneouslywith the readout of the pattern data PAD and is provided to the timinggenerator 133, wherein the rate signal RATE representative of the testperiod is generated from the clock signal CLK. The rate signal RATE isdelayed by very short time intervals corresponding to the delay controldata DCT to produce various timing signals, which are applied to theformatter 132, the analog comparator 104A and the logic comparator 134,thereby defining the timing for respective comparison, the timing forrise and fall of the pattern signal, and so forth.

Upon each detection of a mismatch by the logic comparator 134, a signalof H logic, for instance, which represents a failure, is written in thefailure memory 143 at a failure occurrence address. In an idle timeduring the test or at the end of the test, the failure data (testresults) thus stored in the failure memory 143 is sent via a memory busMBUS and the serial data transceiver 131 to the electro-optic converterEO2 for conversion into an optical signal TXX, which is sent over theoptical fiber OPF5 to the tester mainframe 200.

Effect of the Invention

As described above, according to the present invention, the data, clockand other signals, which are exchanged between the tester mainframe 200and the test head 100, are all transmitted over optical fibers. Thediameter of such an optical fiber is approximately 500 mμφ at thelargest and is sufficiently smaller than the electric cable.Accordingly, even if the number of optical fibers used is the same asthe number of conventional electric cables, the bundle of optical fibersis smaller in diameter than the bundle of electric cables. Furthermore,since the optical fibers are lighter than the electric cables, thebundle of optical fibers is lightweight and easy to handle.

By using the serial data transceivers 111A and 131 as shown in FIG. 9 or11, the number of cables used can be reduced. In particular, theprovision of the pattern memory 142, the timing memory 141 and thefailure memory 143 as depicted in FIG. 11 makes it possible to transmitdifferent signals over common optical fibers. Hence, the number ofoptical fibers used for each terminal of the DUT can be reduced down toabout six as shown in FIG. 11. This leads to reduction of the diameterof the cable group 300 that interconnects the tester mainframe 200 andthe test head 100.

Since the optical fiber does not much attenuate light and is free fromleakage of light, it is possible to keep the tester mainframe 200 andthe test head 100 separated far apart. Accordingly, the tester mainframe200 that generate a large amount of heat can be placed in a roomdifferent from that where the test head 100 is placed, or only the testhead 100 can be disposed in a clean room, for instance. Besides, sinceoptical signals are used to exchange various signals, there is not needof providing a terminating resistor in each signal transmission line.This also present an advantage of offering a tester of small heatgeneration.

It will be apparent that many modifications and variations may beeffected without departing from the scope of the novel concepts of thepresent invention.

What is claimed is:
 1. An integrated circuit device tester which, underthe control of a control processor, generates pattern data andexpectation data by a pattern generator, formats said pattern data by aformatter into a predetermined pattern waveform, applies said patternwaveform by a driver to an IC device under test at a reference voltage,compares a response signal from said IC device under test by an analogcomparator with a reference logical level to make a logical decision,compares the decided logic by a logic comparator with expectation datafrom said pattern generator to decide whether or not said IC under testis defective or nondefective, and writes failure data in a failurememory, said IC device tester comprising:a tester mainframe providedwith said control processor; first serial data transceiver meansprovided in said tester mainframe, for outputting data, as serial data,which is used to set said reference voltage for said driver and saidreference logical level for said analog comparator; electro-opticconverter means provided in said tester mainframe, for converting saidserial data to an optical signal; a test head provided with said driverfor applying a test pattern to said IC device under test and an analogcomparator for deciding the logic of its response; opto-electricconverter means provided in said test head, for converting said opticalsignal to serial data of an electric signal; second serial datatransceiver means provided in said test head, for converting said serialdata to parallel reference voltage data and parallel reference logicallevel data; D/A converter means provided in said test head, forconverting said parallel reference voltage data and said parallelreference logical level data to an analog reference voltage and areference logical level and for setting them in said driver and saidanalog comparator, respectively; and optical fiber means forinterconnecting said electro-optic converter means and saidopto-electric converter means.
 2. The tester of claim 1, wherein saidsecond serial data transceiver means includes register means for holdingreceived serial data and outputting it as various setting parallel data.3. The tester of claim 2, which further comprises a DC test unit in saidtest head and in which a control signal to said DC test unit istransmitted as an optical serial signal from said tester mainframe tocontrol said DC test unit to conduct a DC test of said IC device undertest.
 4. The tester of claim 3, wherein said second serial datatransceiver means stores data set for each terminal and DC test resultsin said register means of said test head and transmits said set data andsaid DC test results as optical serial signals to said tester mainframe.5. The tester of claim 4, wherein a pattern signal to be applied to saidIC device under test is fed as an optical signal for each terminal ofsaid IC device under test from said tester mainframe to said test headand is applied to said IC device under test via said driver provided insaid test head; a signal read out of said IC device under test ischecked by said analog comparator to decide whether it has a normal H-or L-logic voltage; and the decision result is converted by saidelectro-optic converter means into an optical serial signal for saideach terminal of said IC device under test and sent via said opticalfiber means to said tester mainframe.
 6. The tester of claim 3, whereinthird serial data transceiver means, said formatter and said logiccomparator are provided in said test head in correspondence with eachterminal of said IC device under test; digital pattern data is sent as aoptical serial signal for said each terminal from said tester mainframeto said test head and is received and converted therein by said thirdserial data transceiver means to parallel pattern data; said parallelpattern data is converted by said formatter to an analog pattern signal;said pattern signal is applied via said driver to said each terminal; asignal read out of said IC device under test is checked by said analogcomparator to decide whether its logical level is normal or not; thedecision result is subjected to a logical comparison by said logiccomparator with digital expectation pattern data from said testermainframe; and the logical comparison result is sent as an opticalserial signal to said tester mainframe via said third serial datatransceiver means.
 7. The tester of claim 6, wherein said test head isprovided with a timing generator; digital timing data sent as an opticalserial signal is provided to said timing generator after being convertedby said third serial data transceiver means to parallel signals; andoperations of said formatter, said logic comparator and said analogcomparator are controlled following a timing signal from said timinggenerator.
 8. The tester of claim 3, wherein said test head is providedwith a pattern memory, a failure memory and a timing memory; patterndata and timing data sent as optical signals from said tester mainframeto said pattern memory and said timing memory are prestored therein; atthe same time as a test start, said pattern data and said timing dataare read out from said pattern memory and said timing memory andprovided to said formatter and said timing generator to generatetherefrom a pattern signal and a timing signal; a functional test ofsaid IC device is conducted using said pattern signal and said timingsignal; the results of said functional test are obtained by said logiccomparator and stored in said failure memory; and said stored data issent as an optical signal to said tester mainframe.
 9. An integratedcircuit device tester which, under the control of a control processor,generates pattern data and expectation data by a pattern generator,formats said pattern data by a formatter into a predetermined patternwaveform, applies said pattern waveform by a driver to an IC deviceunder test at a reference voltage, compares a response signal from saidIC device under test by an analog comparator with a reference logicallevel to make a logical decision, compares the decided logic by a logiccomparator with expectation data from said pattern generator to decidewhether or not said IC under test is defective or nondefective, andwrites failure data in a failure memory, said IC device testercomprising:a tester mainframe provided with said control processor, saidpattern generator, said formatter, said logic comparator and saidfailure memory; first electro-optic converter means provided in saidtester mainframe, for converting an output test pattern waveform fromsaid formatter to an optical signal; a test head provided with saiddriver and said analog comparator; first opto-electric converter meansprovided in said test head, for converting a test pattern waveformprovided thereto as an optical signal into a test pattern waveform of anelectric signal and for applying it to said driver; second electro-opticconverter means provided in said test head, for converting the result ofcomparison by said analog comparator into an optical signal; secondopto-electric converter means provided in said tester mainframe, forconverting said comparison result provided thereto as said opticalsignal into an electric signal and for applying it to said logiccomparator; first optical fiber means interconnecting the output of saidsecond electro-optic converter means and the input of said firstopto-electric converter means, for transmitting a test pattern opticalsignal from the former to the latter; second optical fiber meansinterconnecting the output of said second electro-optic converter meansand the input of said second opto-electric converter means, fortransmitting a comparison-result optical signal from the former to thelatter; first serial data transceiver means provided in said testermainframe, for outputting, as serial data, data for setting saidreference voltage for said driver and said reference logical level forsaid analog comparator; third electro-optic converter means provided insaid tester mainframe, for converting said serial data to an opticalsignal; third opto-electric converter means provided in said test head,for converting said optical signal to serial data of an electric signal;second serial data transceiver means provided in said test head, forreceiving said serial data and outputting it as parallel referencevoltage data and as parallel reference logical level data; D/A convertermeans provided in said test head, for converting said parallel referencevoltage data and said parallel reference logical level data to an analogreference voltage and an analog reference logical level and for settingthem in said driver and said analog comparator, respectively; and thirdoptical fiber means interconnecting said third electro-optic convertermeans and said third opto-electric converter means.
 10. The tester ofclaim 9, wherein said second serial data transceiver means includesregister means for holding received serial data and for outputting it asparallel data for various setting.
 11. The tester of claim 10, whichfurther comprises a DC test unit in said test head and in which acontrol signal to said DC test unit is transmitted as an optical serialsignal from said tester mainframe to control said DC test unit toconduct a DC test of said IC device under test.
 12. The tester of claim11, wherein said second serial data transceiver means stores data setfor each terminal of said IC device under test and DC test results insaid register means of said test head and transmits said set data andsaid DC test results as optical serial signals to said tester mainframe.13. The tester of claim 3, 4, 11, or 12, which further comprises a relaymatrix provided in said test head, for selectively connecting the outputof said driver and the output of said DC test unit to said IC deviceunder test.